EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 466

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Power Source of Various I/O Standards
Power Source of
Various I/O
Standards
Quartus II
Software
Support
4–38
Stratix Device Handbook, Volume 2
For Stratix and Stratix GX devices, the I/O standards are powered by
different power sources. To determine which source powers the input
buffers, see
You specify which programmable I/O standards to use for Stratix and
Stratix GX devices with the Quartus II software. This section describes
Quartus II implementation, placement, and assignment guidelines,
including
■
■
■
■
■
■
Compiler Settings
You make Compiler settings in the Compiler Settings dialog box
(Processing menu). Click the Chips & Devices tab to specify the device
family, specific device, package, pin count, and speed grade to use for
your design.
2.5V/3.3V LVTTL
PCI/PCI-X 1.0
AGP
1.5V/1.8V
GTL
GTL+
SSTL
HSTL
CTT
LVDS
LVPECL
PCML
HyperTransport
Table 4–13. The Relationships Between Various I/O Standards and the
Power Sources
Compiler Settings
Device & Pin Options
Assign Pins
Programmable Drive Strength Settings
I/O Banks in the Floorplan View
Auto Placement & Verification
Table
I/O Standard
4–13. All output buffers are powered by V
Power Source
V
V
V
V
V
V
V
V
V
V
V
V
V
CCINT
CCINT
CCINT
CCINT
CCINT
CCINT
CCINT
CCINT
CCINT
CCIO
CCIO
CCIO
CCIO
Altera Corporation
CCIO
June 2006
.