EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 459

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
June 2006
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Figure 4–21. Legal Pin Placement
Note to
(1)
VREF Pad Placement Guidelines
Restrictions on the placement of single-ended voltage-referenced I/O
pads with respect to VREF pads help maintain an acceptable noise level
on the V
the VREF rail. The following guidelines are for placing single-ended pads
in Stratix devices.
Input Pins
Each VREF pad supports a maximum of 40 input pads with up to 20 on
each side of the VREF pad.
Output Pins
When a voltage referenced input or bidirectional pad does not exist in a
bank, there is no limit to the number of output pads that can be
implemented in that bank. When a voltage referenced input exists, each
VREF pad supports 20 outputs for thermally enhanced FineLine BGA
and thermally enhanced BGA cavity up packages or 15 outputs for Non-
thermally enhanced cavity up and non-thermally enhanced
FineLine BGA packages.
For flip-chip packages, there are no restrictions for placement of
single-ended input signals with respect to differential signals (see
Figure
only be placed four or more pads away from a differential pad.
Single-ended outputs and bidirectional pads may only be placed five
or more pads away from a differential pad (see
regardless of package type.
Input pads on a flip-chip packages have no restrictions.
Input, Output,
Bidirectional
Figure
CCIO
4–21). For wire-bond packages, single ended input pads may
Wirebond
supply and to prevent output switching noise from shifting
4–21:
Input
Selectable I/O Standards in Stratix & Stratix GX Devices
FlipChip
Input
Differential Pin
Note (1)
Stratix Device Handbook, Volume 2
Figure
Input
Input, Output,
Bidirectional
4–21),
4–31
®