EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 309

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Revision History
Altera Corporation
Chapter
1
September 2004, v3.1
April 2004, v3.0
July 2005, v3.2
Date/Version
This section provides information on the different types of phase-lock
loops (PLLs). The feature-rich, enhanced PLLs assist you in managing
clocks internally and also have the ability to drive off-chip to control
system-level clock networks. The fast PLLs offer general-purpose clock
management with multiplication and phase shifting as well as
high-speed outputs to manage the high-speed differential I/O interfaces.
This chapter contains detailed information on the features, the
interconnections to the core and off-chip, and the specifications for both
types of PLLs.
This section contains the following:
■
The table below shows the revision history for
Chapter 1, General-Purpose PLLs in Stratix & Stratix GX Devices
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Removed information regarding delay shift (time delay elements).
Updated
Updated
Updated
Updated
Updated
Updated Note 1 in
Updated Note 1 in
Updated
Changed PCI-X to PCI-X 1.0 throughout volume.
Note 3 added to columns 11 and 12 in
Deleted “Stratix GX Clock Input Sources for Enhanced and Fast PLLs”
table.
Deleted “Stratix GX Global and Regional Clock Output Line Sharing for
Enhanced and Fast PLLS” table.
Deleted “Stratix GX CLK and FPLLCLK Input Pin Connections to Global
& Regional Clock Networks” table.
Changed
Updated notes to
Added
Clock Switchover section has been moved to AN 313.
Changed
Table
Table
“Clock Switchover”
Figure
“Control Signals”
Table
Table 1–12 on page
CLK
RCLK
1–7.
checkmarks in
1–8.
1–16.
1–22.
values in
Table
Table 1–17 on page
Table 1–21 on page
1–3. and
Figures 1–20
Changes Made
section.
section.
1–34.
Table
Figure
Section I. Clock
1–14.
Table
1–32.
1–48.
and 1–22.
1–3.
Management
Chapter
1–1.
1.
Section I–1