EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 717

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
f
This section describes configuration and remote system upgrade. This
section also provides configuration information for all of the supported
configuration schemes for Stratix
use either a microprocessor, configuration device, or download cable.
There is detailed information on how to design with Altera
configuration devices which includes information on how to manage
multiple configuration files and access the on-chip FLASH memory
space. The last chapter shows you how to perform remote and local
upgrades for your designs.
This section contains the following chapters:
■
■
For information on Altera enhanced configuration devices, see the
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet chapter
in the Configuration Handbook, Volume 2.
Chapter 11, Configuring Stratix & Stratix GX Devices
Chapter 12, Remote System Configuration with Stratix & Stratix GX
Devices
Configuration & Upgrades
Section VI. System
®
devices. These configuration schemes
®
Section VI–1
enhanced