EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 721

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
functionality while the system is in operation by reconfiguring the device.
You can also perform in-field upgrades by distributing a new
programming file to system users.
The following sections describe the MSEL[2..0], VCCSEL, PORSEL, and
nIO_PULLUP pins used in Stratix and Stratix GX device configuration.
MSEL[2..0] Pins
You can select a Stratix or Stratix GX device configuration scheme by
driving its MSEL2, MSEL1, and MSEL0 pins either high or low, as shown
in
The MSEL[] pins can be tied to V
ground.
V
You can configure Stratix and Stratix GX devices using the 3.3-, 2.5-, 1.8-,
or 1.5-V LVTTL I/O standard on configuration and JTAG input pins.
VCCSEL is a dedicated input on Stratix and Stratix GX devices that selects
between 3.3-V/2.5-V input buffers and 1.8-V/1.5-V input buffers for
dedicated configuration input pins. A logic low supports 3.3-V/2.5-V
signaling, and a logic high supports 1.8-V/1.5-V signaling. A logic high
can also support 3.3-V/2.5-V signaling. VCCSEL affects the configuration
Notes to
(1)
(2)
(3)
FPP configuration
PPA configuration
PS configuration
Remote/local update FPP
Remote/local update PPA
Remote/local update PS
JTAG-based configuration
Table 11–2. Stratix & Stratix GX Device Configuration Schemes
CCSEL
Table
These schemes require that you drive a secondary pin RUnLU to specify whether
to perform a remote update or local update.
Do not leave MSEL pins floating. Connect them to V
support the non-JTAG configuration scheme used in production. If only JTAG
configuration is used you should connect the MSEL pins to ground.
JTAG-based configuration takes precedence over other configuration schemes,
which means the MSEL pins are ignored.
Pins
11–2.
Table
11–2:
Description
(1)
(1)
(1)
(3)
CCIO
Configuring Stratix & Stratix GX Devices
of the I/O bank they reside in or
Stratix Device Handbook, Volume 2
MSEL2
(2)
0
0
0
1
1
1
C C I O
or GND. These pins
MSEL1
(2)
0
0
1
0
0
1
MSEL0
(2)
0
1
0
0
1
0
11–3