EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 500

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Receiver Data Realignment
Figure 5–20. Realignment Circuit TXLOADEN Signal Control
Note to
(1)
5–28
Stratix Device Handbook, Volume 2
PLL Output
This figure does not show additional realignment circuitry.
Figure
5–20:
Counter Circuitry
8
SYNC
TXLOADEN signal is generated by the v counter, and when the v counter
is used for realignment, the TXLOADEN signal is generated by the k
counter, as shown in
Realignment Implementation
The realignment signal (SYNC) is used for data realignment and
reframing. An external pin (RX_DATA_ALIGN) or an internal signal
controls the rx_data_align node end. When the rx_data_align
node end is asserted high for at least two low-frequency clock cycles, the
RXLOADEN signal is delayed by one high-frequency clock period and the
parallel bits shift by one bit.
between the high-frequency clock, the RXLOADEN signal, and the parallel
data.
÷ k
÷ v
÷ l
Realignment CLK
Realignment CLK
Realignment
Realignment
Circuit
Circuit
Data
Data
Sync S1
Sync S2
Figure
5–20.
Figure 5–21
Note (1)
Clock
Distribution
Circuitry
shows the timing relationship
CLK1 LVDS
Circuitry
×1 CLK1 to logic array
TXLOADEN
RXLOADEN
×1 CLK2 to logic array
CLK2 LVDS
Circuitry
GCLK/LCLK
Altera Corporation
July 2005