EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 413

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 3–8. DQS & DQSn Pins & the DQS Phase-Shift Circuitry
Notes to
(1)
(2)
Altera Corporation
June 2006
DQS
Pin
Δ t
There are up to 10 DQS and DQSn pins available on the top or the bottom of the Stratix and Stratix GX devices.
Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed
the phase circuitry on the bottom of the device. The reference clock can also be used in the logic array.
Figure
DQS
Pin
Δ t
3–8:
f
DQS
Pin
Δ t
DQS
Pin
Δ t
The phase-shift circuitry is only used during read transactions where the
DQS pins are acting as input clocks or strobes. The phase-shift circuitry
can shift the incoming DQS signal by 0°, 72°, and 90°. The shifted DQS
signal is then inverted and used as a clock or a strobe at the DQ IOE input
registers.
Refer to the DC & Switching Characteristics chapter in volume 1 of the
Stratix Device Handbook for frequency limits regarding the 72 and 90°
phase shift for DQS.
The DQS phase-shift circuitry is bypassed when 0° shift is chosen. The
routing delay between the pins and the IOE registers is matched with
high precision for both the DQ and DQS signal when the 72° or 90° phase
shift is used. With the 0° phase shift, the skew between DQ and the DQS
signals at the IOE register has been minimized. See
Quartus II software reported number on the DQ and DQS path to the IOE
when the DQS is set to 0° phase shift.
Table 3–4. Quartus II Reported Number on the DQS Path to the
IOE
Speed Grade
DQS
Pin
Δ t
Note (1)
-5
-6
-7
CLK[15..12]
Phase Shift
Reference
Circuit
External Memory Interfaces in Stratix & Stratix GX Devices
(2)
DQ2IOE
0.908
0.956
1.098
DQS
Pin
Δ t
DQS
Note (1)
Pin
Δ t
Stratix Device Handbook, Volume 2
DQS
Pin
Δ t
DQS2IOE
1.008
1.061
1.281
DQS
Δ t
Pin
Table 3–4
DQS
Pin
Δ t
DQS Bus
for the
Unit
Compensated
Delay Element
ns
ns
ns
3–17