EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 329

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 1–8. Open- & Closed-Loop Response Bode Plots
Altera Corporation
July 2005
Open-Loop Reponse Bode Plot
Closed-Loop Reponse Bode Plot
Gain
Gain
0 dB
A high-bandwidth PLL provides a fast lock time and tracks jitter on the
reference clock source, passing it through to the PLL output. A low-
bandwidth PLL filters out reference clock jitter, but increases lock time.
Stratix device enhanced PLLs allow you to control the bandwidth over a
General-Purpose PLLs in Stratix & Stratix GX Devices
Frequency
Frequency
Increasing the PLL's
bandwidth in effect pushes
the open loop response out.
Stratix Device Handbook, Volume 2
1–19