HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 80

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

Chapter 10: Analog Capture Circuit
80
AD_CONV
SPI_MISO
SPI_SCK
AD_CONV
SPI_MISO
SPI_SCK
Spartan-3E
Master
FPGA
UCF Location Constraints
AD_CONV
SPI_SCK
SPI_MISO
4ns min
Sample
point
3ns
Z
Figure 10-7
SPI slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC
leaves the SPI_MISO signal in the high-impedance state. Otherwise, the ADC blocks
communication to the other SPI peripherals. As shown in
communications sequence. The ADC 3-states its data output for two clock cycles before
and after each 14-bit data transfer.
Figure 10-8
including the I/O pin assignment and I/O standard used.
AD_CONV
SPI_MISO
D
SPI_SCK
Converted data is presented with a latency of one sample.
The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV.
The converted values is then presented after the next AD_CONV pulse.
0
13
Channel 0
1
D
NET
NET
NET
Figure 10-6: Analog-to-Digital Conversion Interface
1
High-Z
D
2
"AD_CONV"
"SPI_SCK"
"SPI_MISO"
D
Channel 1
Figure 10-7: Detailed SPI Timing to ADC
3
The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles
shows detailed transaction timing. The AD_CONV signal is not a traditional
provides the User Constraint File (UCF) constraints for the amplifier interface,
Figure 10-8: UCF Location Constraints for the ADC Interface
D
4
3
2
D
5
Channel 1
30
D
6
LOC
LOC
LOC
D
7
D
= "P11" |
= "U16" |
= "N10" |
8
2
www.xilinx.com
3
D
Channel 0
0
9
31
D
Slave: LTC1407A-1 A/D Converter
10
13
D
13
11
Channel 1
D
IOSTANDARD
IOSTANDARD
IOSTANDARD
1
12
D
4
8ns
13
32
Z
D
12
0
Spartan-3E FPGA Starter Kit Board User Guide
D
1
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 ;
D
0
5
2
19.6ns min
D
33
6ns
3
45ns min
D
11
4
D
Figure
0
5
Channel 0
D
UG230 (v1.2) January 20, 2011
6
6
SLEW
SLEW
D
34
7
10-6, use a 34-cycle
D
8
= SLOW |
= SLOW |
D
Sample
9
point
D
High-Z
10
UG230_c10_06_022306
UG230_c10_05_030306
D
11
DRIVE
DRIVE
D
12
13
Channel 0
D
13
Z
= 6 ;
= 8 ;
R