HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 118

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

Chapter 15: Expansion Connectors
Table 15-1: Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3) (Continued)
118
FX2_CLKOUT
Signal Name
FX2_IO30
FX2_IO31
FX2_IO32
FX2_IO33
FX2_IO34
FX2_IO39
FX2_IP35
FX2_IP36
FX2_IP37
FX2_IP38
FX2_IP40
GND
GND
5.0V
5.0V
Compatible Board
Mating Receptacle Connectors
Differential I/O
FPGA Pin
GND
GND
The following board is compatible with the FX2 connector on the Spartan-3E Starter Kit
board:
•
The Spartan-3E Starter Kit board uses a Hirose FX2-100P-1.27DS header connector. The
header mates with any compatible 100-pin receptacle connector, including board-mounted
and non-locking cable connectors.
The Hirose FX2 connector, header J3, supports up to 15 differential I/O pairs and two
input-only pairs using either the LVDS or RSDS I/O standards, as listed in
I/O pairs support differential input termination (DIFF_TERM) as described in the
Spartan-3E data sheet. Select pairs have optional landing pads for external termination
resistors.
These signals are not routed with matched differential impedance, as would be required
for ultimate performance. However, all traces have similar lengths to minimize skew.
A11
D12
A15
D10
C12
B15
C15
B11
C4
A8
G9
C3
VDEC1 Video Decoder Board from Digilent, Inc.
http://www.digilentinc.com/Products/Detail.cfm?Prod=VDEC1
Shared Header Connections
LED
J1
J2
www.xilinx.com
JP4
J6
(top)
FX2 Connector
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A
Spartan-3E FPGA Starter Kit Board User Guide
(bottom)
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
B
UG230 (v1.2) January 20, 2011
FPGA Pin
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E10
D9
Signal Name
FX2_CLKIN
FX2_CLKIO
Table
SHIELD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
5.0V
15-2. All
R