HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 27

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

Configuration Mode Jumpers
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
R
The configuration mode jumpers determine which configuration mode the FPGA uses
when power is first applied, or whenever the PROG button is pressed.
The DONE pin LED lights when the FPGA successfully finishes configuration.
Pressing the PROG button forces the FPGA to restart its configuration process.
The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration
storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial
mode.
The 64-macrocell XC2C64A CoolRunner™-II CPLD provides additional programming
capabilities and flexibility when using the BPI Up, BPI Down, or MultiBoot configuration
modes and loading the FPGA from the StrataFlash parallel Flash PROM. The CPLD is user-
programmable.
As shown in
mode. Inserting a jumper grounds the associated mode pin. Insert or remove individual
jumpers to select the FPGA’s configuration mode and associated configuration memory
source.
Table 4-1: Spartan-3E Configuration Mode Jumper Settings (Header J30 in
Figure
Configuration
Master Serial
SPI
(see
Chapter 12,
“SPI Serial
Flash”)
BPI Up
(see
Chapter 11,
“Intel
StrataFlash
Parallel NOR
Flash
PROM”)
Mode
4-2)
Table
Mode Pins
M2:M1:M0
4-1, the J30 jumper block settings control the FPGA’s configuration
0:0:0
1:1:0
0:1:0
www.xilinx.com
FPGA Configuration Image Source
Platform Flash PROM
SPI Serial Flash PROM starting at
address 0
StrataFlash parallel Flash PROM,
starting at address 0 and
incrementing through address
space. The CPLD controls address
lines A[24:20] during BPI
configuration.
Configuration Mode Jumpers
Jumper Settings
M0
M1
M2
M0
M1
M2
M0
M1
M2
J30
J30
J30
27