HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 161

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

Example User Constraints File (UCF)
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
#####################################################
### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE
#####################################################
# ==== Analog-to-Digital Converter (ADC) ====
#
NET "AD_CONV"
# ==== Programmable Gain Amplifier (AMP) ====
#
NET "AMP_CS"
NET "AMP_DOUT"
NET "AMP_SHDN"
# ==== Pushbuttons (BTN) ====
NET "BTN_EAST"
NET "BTN_NORTH" LOC = "V4"
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL
NET "BTN_WEST"
# ==== Clock inputs (CLK) ====
NET "CLK_50MHZ" LOC = "C9"
#
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
NET "CLK_AUX"
NET "CLK_SMA"
# ==== Digital-to-Analog Converter (DAC) ====
#
NET "DAC_CLR"
NET "DAC_CS"
# ==== 1-Wire Secure EEPROM (DS)
NET "DS_WIRE"
# ==== Ethernet PHY (E) ====
NET "E_COL"
NET "E_CRS"
NET "E_MDC"
some connections shared with SPI Flash, DAC, ADC, and AMP
some connections shared with SPI Flash, DAC, ADC, and AMP
Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
some connections shared with SPI Flash, DAC, ADC, and AMP
R
LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW
LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW
LOC = "U4" | IOSTANDARD = LVTTL
LOC = "U6"
LOC = "U13" | IOSTANDARD = LVCMOS33 ;
LOC = "P9"
LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW
LOC = "N7"
LOC = "E18" | IOSTANDARD = LVCMOS33 ;
LOC = "P7"
LOC = "H13" | IOSTANDARD = LVTTL
LOC = "D18" | IOSTANDARD = LVTTL
LOC = "B8"
LOC = "A10" | IOSTANDARD = LVCMOS33 ;
| IOSTANDARD = LVCMOS33 ;
| IOSTANDARD = LVCMOS33 | SLEW = SLOW
| IOSTANDARD = LVCMOS33 | SLEW = SLOW
| IOSTANDARD = LVCMOS33 | SLEW = SLOW
| IOSTANDARD = LVTTL
| IOSTANDARD = LVCMOS33 ;
| IOSTANDARD = LVCMOS33 ;
www.xilinx.com
| SLEW = SLOW
| PULLDOWN ;
| PULLDOWN ;
| PULLDOWN ;
| PULLDOWN ;
| DRIVE = 8 ;
| DRIVE = 8 ;
| DRIVE = 8 ;
| DRIVE = 8 ;
| DRIVE = 6 ;
| DRIVE = 6 ;
| DRIVE = 6 ;
Appendix B
161