HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 113

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

MicroBlaze Ethernet IP Cores
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
R
Table 14-1: FPGA Connections to the LAN83C185 Ethernet PHY (Continued)
The Ethernet PHY is primarily intended for use with MicroBlaze applications. As such, an
Ethernet MAC is part of the EDK Platform Studio’s Base System Builder. Both the full
Ethernet MAC and the Lite version are available for evaluation, as shown in
The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for
applications that do not require support for interrupts, back-to-back data transfers, and
statistics counters.
The Ethernet MAC core requires design constraints to meet the required performance.
Refer to the OPB Ethernet MAC data sheet (v1.02) for details. The OPB bus clock frequency
must be 65 MHz or higher for 100 Mbps Ethernet operations and 6.5 MHz or faster for
10 Mbps Ethernet operations.
Signal Name
E_RX_CLK
E_MDIO
E_MDC
E_COL
E_CRS
Figure 14-3: Ethernet MAC IP Cores for the Spartan-3E Starter Kit Board
FPGA Pin
Number
U13
V3
U6
U5
P9
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Receive Clock. 25 MHz in 100Base-TX mode, and 2.5 MHz in
10Base-T mode.
Carrier Sense
MII Collision Detect.
Management Clock. Serial management clock.
Management Data Input/Output.
Function
MicroBlaze Ethernet IP Cores
UG230_c14_03_022706
Figure
14-3.
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