HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 44

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

Chapter 5: Character LCD Screen
Character LCD Interface Signals
Voltage Compatibility
Interaction with Intel StrataFlash
44
Table 5-1
Table 5-1: Character LCD Interface
The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However,
the FPGA’s output levels are recognized as valid Low or High logic levels by the LCD. The
LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by
the FPGA meet the 5V TTL voltage level requirements.
The 390Ω series resistors on the data lines prevent overstressing on the FPGA and
StrataFlash I/O pins when the character LCD drives a High logic value. The character LCD
drives the data lines when LCD_RW is High. Most applications treat the LCD as a write-
only peripheral and never read from from the display.
As shown in
lines SF_D<11:8>. As shown in
application usage in the design. When the StrataFlash memory is disabled (SF_CE0 =
High), then the FPGA application has full read/write access to the LCD. Conversely, when
LCD read operations are disabled (LCD_RW = Low), then the FPGA application has full
read/write access to the StrataFlash memory
Table 5-2: LCD/StrataFlash Control Interaction
Notes:
1. ‘X’ indicates a don’t care, can be either 0 or 1.
SF_CE0
Signal Name
X
X
1
SF_D<11>
SF_D<10>
LCD_RW
SF_D<9>
SF_D<8>
LCD_RS
LCD_E
shows the interface character LCD interface signals.
SF_BYTE LCD_RW
Figure
X
X
0
5-1, the four LCD data signals are also shared with StrataFlash data
FPGA Pin
www.xilinx.com
M15
M18
P17
R16
R15
L17
L18
X
X
0
Table
StrataFlash disabled. Full read/write access to LCD.
LCD write access only. Full access to StrataFlash.
StrataFlash in byte-wide (x8) mode. Upper address lines
are not used. Full access to both LCD and StrataFlash.
5-2, the LCD/StrataFlash interaction depends on the
Data bit DB7
Data bit DB6
Data bit DB5
Data bit DB4
Read/Write Enable Pulse
0: Disabled
1: Read/Write operation enabled
Register Select
0: Instruction register during write operations. Busy
Flash during read operations
1: Data for read or write operations
Read/Write Control
0: WRITE, LCD accepts data
1: READ, LCD presents data
Spartan-3E FPGA Starter Kit Board User Guide
Operation
Function
SF_D<11:8>
Shared with StrataFlash pins
UG230 (v1.2) January 20, 2011
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