HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 125

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

Connectorless Debugging Port Landing Pads (J6)
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
R
Landing pads for a connectorless debugging port are provided as header J6, shown in
Figure 15-1, page
probe, such as those available from Agilent, provides an interface to a logic analyzer. This
debugging port is intended primarily for the Xilinx ChipScope Pro software with the
Agilent’s FPGA Dynamic Probe. It can, however, be used with either the Agilent or
Tektronix probes, without the ChipScope software, using FPGA Editor’s probe command.
Refer to
probes, and connectors.
Table 15-3
remaining connector pads are unconnected. All 18 FPGA pins are shared with the FX2
connector (J3) and the 6-pin accessory port connectors (J1, J2, and J4). See
page 117
Table 15-3: Connectorless Debugging Port Landing Pads (J6)
Signal Name
FX2_IO10
FX2_IO13
FX2_IO14
FX2_IO17
FX2_IO18
FX2_IO1
FX2_IO2
FX2_IO5
FX2_IO6
FX2_IO9
GND
GND
GND
GND
“Related Resources,” page 126
for more information on how these pins are shared.
provides the connector pinout. Only 18 FPGA pins attach to the connector; the
115. There is no physical connector on the board. Instead a connectorless
FPGA Pin
GND
GND
GND
GND
F11
E11
A4
A6
D7
C7
B4
B6
E9
F9
www.xilinx.com
Connectorless Debugging Port Landing Pads (J6)
A10
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A11
A1
A2
A3
A4
A5
A6
A7
A8
A9
Connectorless
for more information on the ChipScope Pro tool,
Landing Pads
B10
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B11
B1
B2
B3
B4
B5
B6
B7
B8
B9
FPGA Pin
GND
GND
GND
GND
GND
D11
C11
D5
C5
E7
E8
F7
F8
Table 15-1,
Signal Name
FX2_IO11
FX2_IO12
FX2_IO15
FX2_IO16
FX2_IO3
FX2_IO4
FX2_IO7
FX2_IO8
GND
GND
GND
GND
GND
125