C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 82
C8051F700DK
Manufacturer Part Number
C8051F700DK
Description
DEV KIT FOR C8051F700
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051F700-TB.pdf
(1 pages)
2.C8051F700-TB.pdf
(306 pages)
3.C8051F700-TB.pdf
(18 pages)
Specifications of C8051F700DK
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F7x
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1635
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C8051F70x/71x
If CS0BUSY is used to initiate conversions, and then polled to determine if the conversion is finished, at
least one clock cycle must be inserted between setting CS0BUSY to 1 and polling the CS0BUSY bit.
Conversions can be configured to be initiated continuously through one of two methods. CS0 can be con-
figured to convert at a single channel continuously or it can be configured to convert continuously with
auto-scan enabled. When configured to convert continuously, conversions will begin after the CS0BUSY
bit in CS0CF has been set. An interrupt will be generated if CS0 conversion complete interrupts are
enabled by setting the ECSCPT bit (EIE2.0).
The CS0 module uses a method of successive approximation to determine the value of an external capac-
itance. The number of bits the CS0 module converts is adjustable using the CS0CR bits in register
CS0MD2. Conversions are 13 bits long by default, but they can be adjusted to 12, 13, 14, or 16 bits
depending on the needs of the application. Unconverted bits will be set to 0. Shorter conversion lengths
produce faster conversion rates, and vice-versa. Applications can take advantage of faster conversion
rates when the unconverted bits fall below the noise floor.
Note: CS0 conversion complete interrupt behavior depends on the settings of the CS0 accumulator. If CS0 is
82
configured to accumulate multiple conversions on an input channel, a CS0 conversion complete interrupt will
be generated only after the last conversion completes.
Rev. 1.0
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