C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 240

• Manufacturer Part Number: C8051F700DK
• Description: DEV KIT FOR C8051F700
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F700DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F7x
• Processor Series: C8051F7xx
• Interface Type: USB
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F7xx
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1635

C8051F70x/71x
240
Table 30.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) (Continued)
0010
0001
0000 0
0010 0
0001 0
0000 0
Values Read
0
0
0
0
0 X
1 X
0 X
1 X
0 X A slave byte was received.
1 X
1 X
1 X
A slave address + R/W was
received; ACK sent.
Lost arbitration as master;
slave address + R/W received;
ACK sent.
A STOP was detected while
addressed as a Slave Trans-
mitter or Slave Receiver.
Lost arbitration while attempt-
ing a STOP.
Lost arbitration while attempt-
ing a repeated START.
Lost arbitration due to a
detected STOP.
Lost arbitration while transmit-
ting a data byte as master.
Current SMbus State
Rev. 1.0
If Write, Set ACK for first data
byte.
If Read, Load SMB0DAT with
data byte
If Write, Set ACK for first data
byte.
If Read, Load SMB0DAT with
data byte
Reschedule failed transfer
Clear STO.
No action required (transfer
complete/aborted).
Set ACK for next data byte;
Read SMB0DAT.
Set NACK for next data byte;
Read SMB0DAT.
Abort failed transfer.
Reschedule failed transfer.
Abort failed transfer.
Reschedule failed transfer.
Abort failed transfer.
Reschedule failed transfer.
Typical Response Options
Values to
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
Write
0 1
0 X 0100
0 1
0 X 0100
0 X
0 X
0 0
0 1
0 0
0 X
0 X
0 X
0 X
0 X
0 X
0000
0000
0000
0000
1110
1110
1110
1110
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