C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 51

DEV KIT FOR C8051F700

C8051F700DK

Manufacturer Part Number
C8051F700DK
Description
DEV KIT FOR C8051F700
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F700DK

Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F7x
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1635
Table 9.8. Capacitive Sense Electrical Characteristics
V
Parameter
Single Conversion Time
Number of Channels
Capacitance per Code
External Capacitive Load
External Series Impedance
Quantization Noise
Power Supply Current
Notes:
DD
1. Conversion time is specified with the default configuration.
2. RMS Noise is equivalent to one standard deviation. Peak-to-peak noise encompasses ±3.3 standard
3. Includes only current from regulator, CS module, and MCU in suspend mode.
= 1.8 to 3.6 V; T
deviations. The RMS noise value is specified with the default configuration.
A
12
= –40 to +85 °C unless otherwise specified.
1
Wake-on-CS threshold (suspend mode
with regulator and CS module on)
CS module alone, maximum code
CS module bias current, 25 °C
CS0CG = 111b (Default)
CS0CG = 111b (Default)
Default Configuration
13-bit Mode (default)
64-pin Packages
48-pin Packages
32-pin Packages
24-pin Packages
CS0CG = 000b
Peak-to-Peak
output, 25 °C
Conditions
12-bit Mode
14-bit Mode
16-bit Mode
RMS
Rev. 1.0
3
Min
20
21
23
26
C8051F70x/71x
Typ
130
38
27
26
18
29
31
33
38
20
50
90
1
3
Max
42.5
145
500
105
40
45
50
45
50
60
Channels
Units
k
µA
µA
µA
pF
pF
µs
fF
fF
fF
51

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