C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 137
![DEV KIT FOR C8051F700](/photos/9/23/92340/c8051f700dk_sml.jpg)
C8051F700DK
Manufacturer Part Number
C8051F700DK
Description
DEV KIT FOR C8051F700
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051F700-TB.pdf
(1 pages)
2.C8051F700-TB.pdf
(306 pages)
3.C8051F700-TB.pdf
(18 pages)
Specifications of C8051F700DK
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F7x
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1635
- Current page: 137 of 306
- Download datasheet (2Mb)
C8051F70x/71x
21. Interrupts
The C8051F70x/71x includes an extended interrupt system supporting several interrupt sources with two
priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins var-
ies according to the specific version of the device. Each interrupt source has one or more associated inter-
rupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt
condition, the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-
termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE–EIE1). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables
all interrupt sources regardless of the individual interrupt-enable settings.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
Rev. 1.0
137
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