C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 208
C8051F700DK
Manufacturer Part Number
C8051F700DK
Description
DEV KIT FOR C8051F700
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051F700-TB.pdf
(1 pages)
2.C8051F700-TB.pdf
(306 pages)
3.C8051F700-TB.pdf
(18 pages)
Specifications of C8051F700DK
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F7x
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1635
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C8051F70x/71x
SFR Definition 28.33. P5DRV: Port 5 Drive Strength
SFR Address = 0xFE; SFR Page = F
SFR Definition 28.34. P6: Port 6
SFR Address = 0xB2; SFR Page = All Pages
208
Name
Reset
Name
Reset
7:0
7:6
5:0
Bit
Bit
Type
Type
Bit
Bit
Unused
P6[5:0]
P5DRV[7:0]
Name
Name
R
7
0
7
0
Read = 00b; Write = Don’t Care
Port 6 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Drive Strength Configuration Bits for P5.7–P5.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P5.n Output has low output drive strength.
1: Corresponding P5.n Output has high output drive strength.
R
6
0
6
0
Description
5
0
5
1
Rev. 1.0
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
0
4
1
P5DRV[7:0]
R/W
Function
Write
3
0
3
1
P6[5:0]
R/W
2
0
2
1
0: P6.n Port pin is logic
LOW.
1: P6.n Port pin is logic
HIGH.
1
0
1
1
Read
0
0
0
1
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