C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 238
C8051F700DK
Manufacturer Part Number
C8051F700DK
Description
DEV KIT FOR C8051F700
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051F700-TB.pdf
(1 pages)
2.C8051F700-TB.pdf
(306 pages)
3.C8051F700-TB.pdf
(18 pages)
Specifications of C8051F700DK
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F7x
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1635
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C8051F70x/71x
238
Table 30.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) (Continued)
0010 0
0001 0
0000 1
1100
1110
Values Read
Values Read
Table 30.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1)
0
0
0
1 X
1 X
1 X
0 X
0
0
0
1
Lost arbitration while attempt-
ing a repeated START.
Lost arbitration due to a
detected STOP.
Lost arbitration while transmit-
ting a data byte as master.
A master START was gener-
ated.
A master data or address byte
was transmitted; NACK
received.
A master data or address byte
was transmitted; ACK
received.
Current SMbus State
Current SMbus State
Rev. 1.0
Abort failed transfer.
Reschedule failed transfer.
Abort failed transfer.
Reschedule failed transfer.
Abort failed transfer.
Reschedule failed transfer.
Load slave address + R/W into
SMB0DAT.
Set STA to restart transfer.
Abort transfer.
Load next data byte into
SMB0DAT.
End transfer with STOP.
End transfer with STOP and start
another transfer.
Send repeated START.
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
Typical Response Options
Typical Response Options
Values to
Values to
0
1
0
1
0
1
0
1
0
0
0
1
1
0
Write
Write
0 X
0 X
0 X
0 X
0 0
0 0
0 X 1100
0 X
1 X
0 X 1100
1 X
1 X
0 X
0 1
1000
1110
1110
1110
1110
1110
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