C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 168

• Manufacturer Part Number: C8051F700DK
• Description: DEV KIT FOR C8051F700
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F700DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F7x
• Processor Series: C8051F7xx
• Interface Type: USB
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F7xx
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1635

C8051F70x/71x
SFR Definition 25.2. RSTSRC: Reset Source
SFR Address = 0xEF; SFR Page = All Pages
168
Note: Do not use read-modify-write operations on this register
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
FERROR Flash Error Reset Flag.
WDTRSF Watchdog Timer Reset Flag. N/A
MCDRSF Missing Clock Detector
C0RSEF Comparator0 Reset Enable
SWRSF
PINRSF
Unused
PORSF
Name
R
7
0
Unused.
and Flag.
Software Reset Force and
Flag.
Enable and Flag.
Power-On / V
Reset Flag, and V
Reset Enable.
HW Pin Reset Flag.
FERROR
Varies
R
6
Description
DD
C0RSEF
Varies
Monitor
R/W
DD
5
monitor
SWRSF
Varies
R/W
Rev. 1.0
4
Don’t care.
N/A
Writing a 1 enables
Comparator0 as a reset
source (active-low).
Writing a 1 forces a sys-
tem reset.
Writing a 1 enables the
Missing Clock Detector.
The MCD triggers a reset
if a missing clock condition
is detected.
Writing a 1 enables the
V
source.
Writing 1 to this bit
before the V
is enabled and stabilized
may cause a system
reset.
N/A
DD
monitor as a reset
WDTRSF
Varies
Write
R
3
DD
monitor
MCDRSF
Varies
R/W
2
0
Set to 1 if Flash
read/write/erase error
caused the last reset.
Set to 1 if Comparator0
caused the last reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Set to 1 if Watchdog Timer
overflow caused the last
reset.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
Set to 1 anytime a power-
on or V
occurs.
When set to 1 all other
RSTSRC flags are inde-
terminate.
Set to 1 if RST pin caused
the last reset.
PORSF
Varies
R/W
DD
1
Read
monitor reset
PINRSF
Varies
R
0