C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 167

• Manufacturer Part Number: C8051F700DK
• Description: DEV KIT FOR C8051F700
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F700DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F7x
• Processor Series: C8051F7xx
• Interface Type: USB
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F7xx
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1635

25.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this
reset.
25.6. Watchdog Timer Reset
The programmable Watchdog Timer (WDT) can be used to prevent software from running out of control
during a system malfunction. The WDT function can be enabled or disabled by software as described in
Section “26. Watchdog Timer” on page 169. If a system malfunction prevents user software from updating
the WDT, a reset is generated and the WDTRSF bit (RSTSRC.3) is set to 1. The state of the RST pin is
unaffected by this reset.
25.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
25.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.




write operation targets an address above address 0x3DFF.
above address 0x3DFF.
address above 0x3DFF.
Options” on page 149
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a MOVX
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an address
A Program read is attempted above user code space. This occurs when user code attempts to branch to an
A Flash read, write or erase attempt is restricted due to a Flash security setting (see
).
Rev. 1.0
C8051F70x/71x
Section “22.3. Security
167