TMP86C909XB Toshiba, TMP86C909XB Datasheet - Page 75

• Manufacturer Part Number: TMP86C909XB
• Description: EMULATION CHIP FOR TMP86F SDIP
• Manufacturer: Toshiba

Specifications of TMP86C909XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3 Address Trap
7.3 Address Trap
Watchdog Timer Control Register 1
Watchdog Timer Control Register 2
WDTCR1
7.3.1 Selection of Address Trap in Internal RAM (ATAS)
7.3.2 Selection of Operation at Address Trap (ATOUT)
7.3.3 Address Trap Interrupt (INTATRAP)
(0034H)
WDTCR2
(0035H)
traps.
The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address
an instruction in the internal RAM area, clear WDTCR1<ATAS> to “0”. To enable the WDTCR1<ATAS> set-
ting, set WDTCR1<ATAS> and then write D2H to WDTCR2.
setting in WDTCR1<ATAS>.
WDTCR1<ATOUT>.
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap interrupt (INTATRAP) will be generated.
ter flag (IMF).
already accepted, the new address trap is processed immediately and the previous interrupt is held pending.
Therefore, if address trap interrupts are generated continuously without execution of the RETN instruction, too
many levels of nesting may cause a malfunction of the microcontroller.
WDTCR1<ATAS> specifies whether or not to generate address traps in the internal RAM area. To execute
Executing an instruction in the SFR or DBR area generates an address trap unconditionally regardless of the
When an address trap is generated, either the interrupt request or the reset request can be selected by
While WDTCR1<ATOUT> is “0”, if the CPU should start looping for some cause such as noise and an
An address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt mas-
When an address trap interrupt is generated while the other interrupt including a watchdog timer interrupt is
To generate address trap interrupts, set the stack pointer beforehand.
ATOUT
WDTCR2
7
ATAS
7
6
Select address trap generation in
the internal RAM area
Select opertion at address trap
6
Write
Watchdog timer control code
and address trap area control
code
ATAS
5
5
ATOUT
4
4
(WDTEN)
3
0: Generate no address trap
1: Generate address traps (After setting ATAS to “1”, writing the control code
0: Interrupt request
1: Reset request
3
D2H: Enable address trap area selection (ATRAP control code)
4EH: Clear the watchdog timer binary counter (WDT clear code)
B1H: Disable the watchdog timer (WDT disable code)
Others: Invalid
D2H to WDTCR2 is reguired)
Page 64
2
2
(WDTT)
1
1
(WDTOUT)
0
0
(Initial value: **** ****)
(Initial value: **11 1001)
TMP86F409NG
Write
Write
only
only