TMP86C909XB Toshiba, TMP86C909XB Datasheet - Page 132

• Manufacturer Part Number: TMP86C909XB
• Description: EMULATION CHIP FOR TMP86F SDIP
• Manufacturer: Toshiba

Specifications of TMP86C909XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.7 Interrupt Generation
11.8 SEI System Errors
11.8.1 Write collision error
11.8.2 Overflow error
interrupts is generated.
The SEI for the TMP86F409NG uses INTSEI1. When the SESR<SEF> changes state from “0” to “1”, respective
The SEI has the facility to detect following two system errors.
• Write collision error:
• Overflow error:
progress. Because the SEDR register is not configured as dual-buffers when sending data, a write to the SEDR
register directly results in writing to the SEI shift register. Therefore, writing to the SEDR register while trans-
fer is in progress causes a write collision error.
will not be written to the shift register. Because slaves cannot control the timing at which the master starts a
transfer, collision of writes normally occurs on the slave side.
transfer at any time, but in view of SEI logic both the master and slaves have the facility to detect write colli-
sion errors.
that at which the slave processes the transferred data. More specifically, a write collision error occurs in cases
where the slave transfers a new value to the SEDR register when the master already started a shift cycle for the
next byte.
cannot keep abreast with transfer from the master, because the master is shifting out data faster than can be pro-
cessed by the slave. The SEI module uses the SOVF flag (SESR<SOVF>) to detect that data has overflowed.
Collision of writes occurs when an attempt is made to write to the SEDR register while transfer is in
In no case is data transfer stopped in the middle, so that the write data which caused a write collision error
Write collision errors do not normally occur on the master side because the master has the right to perform a
A write collision error tends to occur on the slave side when the master shifts out data at a speed faster than
The transfer bit rate on the SEI bus is determined by the master. A high bit rate causes a problem that a slave
The SOVF flag is set in the following cases:
When the SOVF flag is set, the SEDR register is overwritten with a new data byte.
Note:Please carefully examine the communication processing routine and communication rate when designing
• When the SEI module is set for slave
• When the old data byte remains to be read while a new data byte has been received
When the SEDR register is accessed for write during transfer.
When the new data byte is shift in before the previous data byte is read in slave mode.
your application system.
Table 11-6 SEI Interrupt
SEI interrupt channel 1 (INTSEI1)
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Interrupt generated for SEF
TMP86F409NG