TMP86C909XB Toshiba, TMP86C909XB Datasheet - Page 130

• Manufacturer Part Number: TMP86C909XB
• Description: EMULATION CHIP FOR TMP86F SDIP
• Manufacturer: Toshiba

Specifications of TMP86C909XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11-5 Transfer Format Details where CPHA = 1
SCLK cycle
SCLK
(CPOL = 0)
SCLK
(CPOL = 1)
MOSI
MISO
SECR<SEE>
SS
SEF
• In master mode, transfer is initiated by writing new data to the SEDR register. The new data changes
• In slave mode, unlike in the case of CPHA = 0 format, data can be written to the SEDR (SEI Data Reg-
CPOL=0
CPOL=1
state on the MOSI pin at the first edge of the shift clock. Use BOS (SECR<BOS>) to select whether the
data should be shifted out beginning with the MSB or LSB.
ister) regardless of whether the
In both master and slave modes, the SEF flag (SESR<SEF>) is set after the last shift cycle.
Writing data to the SEDR register while data transfer is in progress causes collision of writes. There-
fore, wait until the SEF flag is set before writing new data to the SEDR register.
Figure 11-3 Transfer Format where CPHA = 1
Communicating (IDLE)
SCLK Level when Not
“H” level
“L” level
1
2
SS
Rising edge of transfer clock
Falling edge of transfer clock
3
pin is “L” or “H”.
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4
Data Shift
5
6
Falling edge of transfer clock
Rising edge of transfer clock
7
Data Sampling
8
Internal
shift clock
TMP86F409NG