TMP86C909XB Toshiba, TMP86C909XB Datasheet - Page 68

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TMP86C909XB

Manufacturer Part Number
TMP86C909XB
Description
EMULATION CHIP FOR TMP86F SDIP
Manufacturer
Toshiba
Datasheet

Specifications of TMP86C909XB

Accessory Type
Adapter
For Use With/related Products
TMP86F SDIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
6.2 Divider Output (
6.2.1 Configuration
6.2.2 Control
Time Base Timer Control Register
buzzer drive. Divider output is from
Data output
Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric
Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other
(0036H)
TBTCR
fc/2
fc/2
fc/2
fc/2
13
12
11
10
The Divider Output is controlled by the Time Base Timer Control Register.
words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not
change the setting of the divider output frequency.
or fs/2
or fs/2
or fs/2
or fs/2
5
4
3
2
Divider output control register
DVOCK
DVOEN
(a) configuration
DVOEN
DVOCK
7
Output latch
A
B
C
D
D
MPX
2
S
Y
TBTCR
Q
6
DVO
Divider output
enable / disable
Divider Output (
frequency selection: [Hz]
DVOCK
DVOEN
)
5
DVO
Figure 6-3 Divider Output
DVO
(DV7CK)
)
pin.
4
(TBTEN)
Page 57
DVO pin
0: Disable
1: Enable
3
00
01
10
11
Port output latch
TBTCR<DVOEN>
DVO pin output
DV7CK = 0
2
NORMAL1/2, IDLE1/2 Mode
fc/2
fc/2
fc/2
fc/2
13
12
10
11
(TBTCK)
1
(b) Timing chart
DV7CK = 1
0
fs/2
fs/2
fs/2
fs/2
5
4
3
2
(Initial value: 0000 0000)
SLEEP1/2
SLOW1/2
TMP86F409NG
Mode
fs/2
fs/2
fs/2
fs/2
5
4
3
2
R/W
R/W

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