TMP86C909XB Toshiba, TMP86C909XB Datasheet - Page 51

• Manufacturer Part Number: TMP86C909XB
• Description: EMULATION CHIP FOR TMP86F SDIP
• Manufacturer: Toshiba

Specifications of TMP86C909XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.5 Software Interrupt (INTSW)
Example 1 :Returning from address trap interrupt (INTATRAP) service program
Example 2 :Restarting without returning interrupt
3.5 Software Interrupt (INTSW)
3.4.3 Interrupt return
3.5.1 Address error detection
is highest prioritized interrupt).
Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW
Use the SWI instruction only for detection of the address error or for debugging.
(In this case, PSW (Includes IMF) before interrupt acceptance is discarded.)
restarting address, during interrupt service program.
rupt can be accepted immediately after the interrupt return instruction is executed.
memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is gener-
ated and an address error is detected. The address error detection range can be further expanded by writing
FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is
fetched from RAM, DBR or SFR areas.
Interrupt return instructions [RETI]/[RETN] perform as follows.
As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to
Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next inter-
Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return inter-
Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service
FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent
PINTxx:
PINTxx:
INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and
PCH are located on address (SP + 1) and (SP + 2) respectively.
rupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example
2).
task is performed but not the main task.
POP
LD
PUSH
(interrupt processing)
RETN
INC
INC
INC
(interrupt processing)
LD
JP
1. Program counter (PC) and program status word
2. Stack pointer (SP) is incremented by 3.
(PSW, includes IMF) are restored from the stack.
WA
WA, Return Address
WA
SP
SP
SP
EIRL, data
Restart Address
[RETI]/[RETN] Interrupt Return
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; Alter stacked data
;
;
; Set IMF to “1” or clear it to “0”
; Jump into restarting address
; Recover SP by 2
;
; RETURN
; Recover SP by 3
TMP86F409NG