TMP86C909XB Toshiba, TMP86C909XB Datasheet - Page 45

• Manufacturer Part Number: TMP86C909XB
• Description: EMULATION CHIP FOR TMP86F SDIP
• Manufacturer: Toshiba

Specifications of TMP86C909XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.2 Interrupt enable register (EIR)
Example 1 :Clears interrupt latches
Example 2 :Reads interrupt latchess
Example 3 :Tests interrupt latches
3.2 Interrupt enable register (EIR)
3.2.1 Interrupt master enable flag (IMF)
3.2.2 Individual interrupt enable flags (EF15 to EF4)
interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Non-
maskable interrupt is accepted regardless of the contents of the EIR.
registers are located on address 003AH and 003BH in SFR area, and they can be read and written by an instructions
(Including read-modify-write instructions such as bit manipulation or operation instructions).
Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to
The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These
While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt
enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled. When
an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable inter-
rupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data,
which was the status before interrupt acceptance, is loaded on IMF again.
The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initial-
ized to “0”.
bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0” dis-
ables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to “0” and
all maskable interrupts are not accepted until they are set to “1”.
"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL
(Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on
interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL
should be executed before setting IMF="1".
The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt.
The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction.
Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding
Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear
IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF
or IL (Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute nor-
mally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulat-
ing EF or IL should be executed before setting IMF="1".
DI
LDW
EI
LD
TEST
JR
(ILL), 1110100000111111B
WA, (ILL)
(ILL). 7
F, SSET
Page 34
; IMF
; IL12, IL10 to IL6
; IMF
; W
; if IL7 = 1 then jump
←
←
←
ILH, A
0
1
←
←
ILL
0
TMP86F409NG