TMP86C909XB Toshiba, TMP86C909XB Datasheet - Page 18

• Manufacturer Part Number: TMP86C909XB
• Description: EMULATION CHIP FOR TMP86F SDIP
• Manufacturer: Toshiba

Specifications of TMP86C909XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2. Operational Description
2.1 CPU Core Functions
2.1.1 Memory Address Map
2.1.2 Program Memory (Flash)
2.1.3 Data Memory (RAM)
The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.
tion register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the
address map.
to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available
against such an area.
The TMP86F409NG memory is composed Flash, RAM, DBR(Data buffer register) and SFR(Special func-
The TMP86F409NG has a 4096 bytes (Address F000H to FFFFH) of program memory (Flash ).
The TMP86F409NG has 512bytes (Address 0040H to 023FH) of internal RAM. The first 192 bytes (0040H
Flash
RAM
DBR
SFR
FFC0
FFDF
FFE0
FFFF
0FFF
003F
023F
0F80
F000
0000
0040
H
H
H
H
H
H
H
H
H
H
H
Figure 2-1 Memory Address Map
64 bytes
bytes
bytes
bytes
4096
512
128
Page 7
Vector table for vector call instructions
(32 bytes)
Vector table for interrupts
(32 bytes)
Flash:
RAM:
DBR:
SFR:
Special function register includes:
I/O ports
Peripheral control registers
Peripheral status registers
System control registers
Program status word
Random access memory includes:
Data memory
Stack
Data buffer register includes:
Peripheral control registers
Peripheral status registers
Program memory
TMP86F409NG
TMP86F409NG
memory