S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 683

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S912XEG128J2MAL

Manufacturer Part Number
S912XEG128J2MAL
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XEG128J2MAL

Rohs
yes
Core
RISC
Processor Series
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
128 KB
Data Ram Size
12 KB
On-chip Adc
Yes
Operating Supply Voltage
5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
8
Data Rom Size
4 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
On-chip Dac
Yes
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S912XEG128J2MAL
Manufacturer:
NXP/恩智浦
Quantity:
20 000
18.3.0.4
Read: Anytime
Write: Anytime
18.3.0.5
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0003
Module Base + 0x0004
PMUX[3:0]
PINTE[3:0]
Reset
Reset
Field
Field
3:0
3:0
W
W
R
R
PIT Multiplex Bits for Timer Channel 3:0 — These bits select if the corresponding 16-bit timer is connected to
micro time base 1 or 0. If PMUX is modified, the corresponding 16-bit timer is switched to the other micro time
base immediately.
0 The corresponding 16-bit timer counts with micro time base 0.
1 The corresponding 16-bit timer counts with micro time base 1.
PIT Time-out Interrupt Enable Bits for Timer Channel 3:0 — These bits enable an interrupt service request
whenever the time-out flag PTF of the corresponding PIT channel is set. When an interrupt is pending (PTF set)
enabling the interrupt will immediately cause an interrupt. To avoid this, the corresponding PTF flag has to be
cleared first.
0 Interrupt of the corresponding PIT channel is disabled.
1 Interrupt of the corresponding PIT channel is enabled.
PIT Multiplex Register (PITMUX)
PIT Interrupt Enable Register (PITINTE)
0
0
0
0
7
7
0
0
0
0
6
6
Figure 18-7. PIT Interrupt Enable Register (PITINTE)
Figure 18-6. PIT Multiplex Register (PITMUX)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 18-5. PITMUX Field Descriptions
Table 18-6. PITINTE Field Descriptions
0
0
0
0
5
5
0
0
0
0
4
4
Description
Description
PINTE3
PMUX3
0
0
3
3
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
PMUX2
PINTE2
0
0
2
2
PMUX1
PINTE1
0
0
1
1
PMUX0
PINTE0
0
0
0
0
683

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