S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 436

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Chapter 10 XGATE (S12XGATEV3)
LSR
Operation
n = RS or IMM4
Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled
with zeros. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
Code and CPU Cycles
436
N:
Z:
V:
C:
LSR RD, #IMM4
LSR RD, RS
N
∆
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected.
Z
∆
old
V
∆
Source Form
^ RD[15]
C
∆
new
0
0
n bits
MC9S12XE-Family Reference Manual Rev. 1.25
0
Address
Mode
IMM4
0
DYA
Logical Shift Right
0
0
0
0
0
0
0
0
RD
n
1
1
Machine Code
RD
RD
RS
IMM4
C
1
1
0
Freescale Semiconductor
1
1
LSR
0
0
1
1
Cycles
P
P