S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 536

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S912XEG128J2MAL

Manufacturer Part Number
S912XEG128J2MAL
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XEG128J2MAL

Rohs
yes
Core
RISC
Processor Series
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
128 KB
Data Ram Size
12 KB
On-chip Adc
Yes
Operating Supply Voltage
5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
8
Data Rom Size
4 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
On-chip Dac
Yes
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S912XEG128J2MAL
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.3.2.2
Read or write: Anytime but reads will always return 0x0000 (1 state is transient).
All bits reset to zero.
14.3.2.3
Read or write: Anytime
All bits reset to zero.
536
Module Base + 0x0001
Module Base + 0x0002
FOC[7:0]
Reset
Reset
Field
7:0
W
W
R
R
OC7M7
FOC7
Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note: A channel 7 event, which can be a counter overflow when TTOV[7] is set or A successful channel 7 output
Timer Compare Force Register (CFORC)
Output Compare 7 Mask Register (OC7M)
0
0
0
7
7
compare overrides any channel 6:0 compares. If a forced output compare on any channel occurs at the
same time as the successful output compare, then the forced output compare action will take precedence
and the interrupt flag will not get set.
OC7M6
FOC6
0
0
0
Figure 14-5. Output Compare 7 Mask Register (OC7M)
6
6
Figure 14-4. Timer Compare Force Register (CFORC)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 14-3. CFORC Field Descriptions
OC7M5
FOC5
0
0
0
5
5
OC7M4
FOC4
0
0
0
4
4
Description
OC7M3
FOC3
0
0
0
3
3
OC7M2
FOC2
0
0
0
2
2
OC7M1
Freescale Semiconductor
FOC1
0
0
0
1
1
OC7M0
FOC0
0
0
0
0
0

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