S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 359

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

10.3.1.1
All module level switches and flags are located in the XGATE Module Control Register
Module Base +0x00000
Read: Anytime
Write: Anytime
Freescale Semiconductor
Reset
XGDBGM
XGFRZM
XGSSM
XGEM
Field
W
R
15
14
13
12
XGEM
15
0
0
XGE Mask — This bit controls the write access to the XGE bit. The XGE bit can only be set or cleared if a "1" is
written to the XGEM bit in the same register access.
Read:
Write:
0 Disable write access to the XGE in the same bus cycle
1 Enable write access to the XGE in the same bus cycle
XGFRZ Mask — This bit controls the write access to the XGFRZ bit. The XGFRZ bit can only be set or cleared
if a "1" is written to the XGFRZM bit in the same register access.
Read:
Write:
0 Disable write access to the XGFRZ in the same bus cycle
1 Enable write access to the XGFRZ in the same bus cycle
XGDBG Mask — This bit controls the write access to the XGDBG bit. The XGDBG bit can only be set or cleared
if a "1" is written to the XGDBGM bit in the same register access.
Read:
Write:
0 Disable write access to the XGDBG in the same bus cycle
1 Enable write access to the XGDBG in the same bus cycle
XGSS Mask — This bit controls the write access to the XGSS bit. The XGSS bit can only be set or cleared if a
"1" is written to the XGSSM bit in the same register access.
Read:
Write:
0 Disable write access to the XGSS in the same bus cycle
1 Enable write access to the XGSS in the same bus cycle
FRZM
XGATE Control Register (XGMCTL)
XG
14
0
0
This bit will always read "0".
This bit will always read "0".
This bit will always read "0".
This bit will always read "0".
= Unimplemented or Reserved
DBGM
XG
13
0
0
SSM
Table 10-2. XGMCTL Field Descriptions (Sheet 1 of 3)
XG
12
0
0
Figure 10-3. XGATE Control Register (XGMCTL)
FACTM
MC9S12XE-Family Reference Manual Rev. 1.25
XG
11
0
0
10
0
0
SWEFM
XG
0
0
9
XGIEM
0
0
8
Description
XGE
0
7
XGFRZ XGDBG XGSS XGFACT
6
0
0
5
0
4
Chapter 10 XGATE (S12XGATEV3)
0
3
Figure
0
0
2
SWEF
XG
1
0
10-3.
XGIE
0
0
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