S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 627

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
16.3.2.16 MSCAN Transmit Error Counter (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
Module Base + 0x000E
Module Base + 0x000F
Write: Unimplemented
Write: Unimplemented
Reset:
Reset:
W
W
R
R
RXERR7
TXERR7
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
0
0
7
7
Figure 16-19. MSCAN Transmit Error Counter (CANTXERR)
Figure 16-18. MSCAN Receive Error Counter (CANRXERR)
RXERR6
TXERR6
= Unimplemented
= Unimplemented
6
0
6
0
MC9S12XE-Family Reference Manual Rev. 1.25
RXERR5
TXERR5
0
0
5
5
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
RXERR4
TXERR4
NOTE
NOTE
4
0
4
0
RXERR3
TXERR3
0
0
3
3
RXERR2
TXERR2
2
0
2
0
Access: User read/write
Access: User read/write
RXERR1
TXERR1
0
0
1
1
RXERR0
TXERR0
0
0
0
0
627
(1)
(1)