SSTUB32865ET/G,518 NXP Semiconductors, SSTUB32865ET/G,518 Datasheet - Page 8

• Manufacturer Part Number: SSTUB32865ET/G,518
• Description: IC REG BUFFER 28BIT 160TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUB32865ET/G,518

• Logic Type: 1:2 Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-TFBGA
• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 2V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 160
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3542-2; 935281691518; SSTUB32865ET/G-T

NXP Semiconductors
7. Functional description
Table 4.
[1]
[2]
Table 5.
SSTUB32865_3
Product data sheet
RESET DCS0
RESET
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Q
DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs.
H
H
H
H
H
H
H
H
H
H
L
0
is the previous state of the associated output.
floating
Function table (each flip-flop)
Parity and standby function table
X or
X or floating
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
DCS0
[2]
7.1 Function table
H
H
H
H
H
X
L
L
L
L
DCS1
floating
[1]
X or
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
[2]
X or floating
DCS1
CSGATEEN
X or floating
H
H
H
H
H
X
L
L
L
L
[1]
X
X
X
X
X
X
X
X
X
H
H
H
L
L
L
Inputs
X or floating
L or H
floating
L or H
L or H
L or H
L or H
L or H
CK
X or
CK
Inputs
Rev. 03 — 27 March 2007
floating
L or H
L or H
L or H
L or H
L or H
X or floating
X or
CK
L or H
CK
Dn, DODTn, DCKEn
X or floating
1.8 V DDR2-800 registered buffer with parity
(D0 to D21)
X or floating
of inputs = H
H
X
H
X
H
X
H
X
H
X
L
L
L
L
L
even
even
even
even
odd
odd
odd
odd
X
X
Qn
Q
Q
Q
Q
Q
Q
Q
H
H
H
H
L
L
L
L
L
0
0
0
0
0
0
0
SSTUB32865
X or floating
PARIN
QCS0
H
H
H
H
L
L
L
L
X
X
Q
Q
Q
Q
Q
H
H
H
H
H
H
L
L
L
L
L
0
0
0
0
0
Outputs
[2]
© NXP B.V. 2007. All rights reserved.
QCS1 QODTn,
Q
Q
Q
Q
Q
H
H
H
H
H
H
L
L
L
L
L
PTYERR
0
0
0
0
0
[1]
PTYERR
PTYERR
Output
H
H
H
H
H
QCKEn
L
L
L
L
Q
Q
Q
Q
Q
H
H
H
H
H
[3][4]
8 of 28
L
L
L
L
L
L
0
0
0
0
0
0
0