SSTUB32865ET/G,518 NXP Semiconductors, SSTUB32865ET/G,518 Datasheet - Page 13

• Manufacturer Part Number: SSTUB32865ET/G,518
• Description: IC REG BUFFER 28BIT 160TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUB32865ET/G,518

• Logic Type: 1:2 Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-TFBGA
• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 2V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 160
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3542-2; 935281691518; SSTUB32865ET/G-T

NXP Semiconductors
SSTUB32865_3
Product data sheet
Fig 6. RESET switches from HIGH to LOW
PARIN
PTYERR
(1) After RESET is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not
RESET
Dn
DCSn
CK
CK
Qn
(1)
floating) for a minimum time of t
(1)
(1)
(1)
INACT(max)
.
RESET to Q
Rev. 03 — 27 March 2007
t
PHL
HIGH, LOW, or Don't care
t
INACT
t
RESET to PTYERR
PLH
1.8 V DDR2-800 registered buffer with parity
HIGH or LOW
SSTUB32865
© NXP B.V. 2007. All rights reserved.
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