SSTUB32865ET/G,518 NXP Semiconductors, SSTUB32865ET/G,518 Datasheet
SSTUB32865ET/G,518
Specifications of SSTUB32865ET/G,518
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SSTUB32865ET/G-T
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SSTUB32865ET/G,518 Summary of contents
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SSTUB32865 1.8 V 28-bit registered buffer with parity for DDR2-800 RDIMM applications Rev. 03 — 27 March 2007 1. General description The SSTUB32865 is a 1.8 V 28-bit register specifically designed for use on ...
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... NXP Semiconductors I Chip-selects minimize power consumption by gating data outputs from changing state I Two additional chip select inputs allow optional flexible enabling and disabling I Supports Stub Series Terminated Logic SSTL_18 data inputs I Differential clock (CK and CK) inputs I Supports LVCMOS switching levels on the control and RESET inputs I Single 1 ...
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... NXP Semiconductors 5. Functional diagram VREF PARIN D0 D21 DCS0 CSGATEEN DCS1 DCS2 DCS3 DCKE0, 2 DCKE1 DODT0, 2 DODT1 RESET CK CK Fig 1. Functional diagram of SSTUB32865 SSTUB32865_3 Product data sheet 1.8 V DDR2-800 registered buffer with parity (CS ACTIVE) PARITY GENERATOR D Q AND 22 R CHECKER Rev. 03 — 27 March 2007 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration for TFBGA160 SSTUB32865_3 Product data sheet 1.8 V DDR2-800 registered buffer with parity SSTUB32865ET/G SSTUB32865ET/S ball A1 index area Transparent top view Rev. 03 — 27 March 2007 SSTUB32865 11 002aac016 © NXP B.V. 2007. All rights reserved. ...
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... NXP Semiconductors VREF SELDR PARIN n. D11 D9 F D18 D12 G CSGATEEN D15 H CK DCS0 J CK DCS1 K RESET D14 L D0 D10 M D17 D16 N D19 D21 P D13 D20 R DODT1 DODT0 T DCKE0 DCKE1 MCL U VREF MCL MCL V 160-ball grid; top view. An empty cell indicates no ball is populated at that grid point. ...
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... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin Ungated inputs DCKE0, DCKE1 U1, U2 DODT0, DODT1 T2, T1 Chip Select gated inputs D0 to D21 M1, B1, B2, C1, C2, D2, D1, E1, E2, F2, M2, F1, G2, R1, L2, H2, N2, N1, G1, P1, R2, P2 Chip Select inputs DCS0, DCS1, J2, K2, H4, K4 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Program inputs CSGATEEN H1 SELDR A2 Clock inputs CK, CK J1, K1 Miscellaneous inputs MCL U3, V2, V3 MCH U5, V5 RESET L1 VREF A1, V1 VDDL D4, E4, E6, F4, G4, K5, N4, N5, P5, P6, R5, R6 VDDR E7, F8, F9, G8, G9, J8, J9, L8, L9, N8, N9, P7, P8 GND D5, D8, D9, E5, E8, E9, F5, ...
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... NXP Semiconductors 7. Functional description 7.1 Function table Table 4. Function table (each flip-flop) [2] [2] RESET DCS0 DCS1 CSGATEEN floating floating floating [ the previous state of the associated output. 0 [2] DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs. ...
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... NXP Semiconductors [1] DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function. [2] PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated correctly. [3] This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. CSGATEEN is ‘ ...
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... NXP Semiconductors functionality is not desired, then the CSGATEEN input can be hardwired to ground, in which case, the set-up time requirement for DCSn would be the same as for the other Dn data inputs. The SSTUB32865 includes a parity checking function. The SSTUB32865 accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the Dn inputs (with either DCSn inputs active) and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW) ...
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... NXP Semiconductors 7.3.4 Power-up sequence The reset function for the SSTUB32865 is similar to that of the SSTU32864 except that the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive clock cycles. RESET DCSn ACT ( PARIN PTYERR HIGH, LOW, or Don't care ...
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... NXP Semiconductors RESET DCSn PDM Qn PARIN PTYERR Unknown input event Fig 5. RESET being held HIGH SSTUB32865_3 Product data sheet PDMSS Output signal is dependent on the prior unknown event Rev. 03 — 27 March 2007 SSTUB32865 1.8 V DDR2-800 registered buffer with parity PHL PLH ...
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... NXP Semiconductors RESET DCSn (1) CK ( (1) PARIN PTYERR (1) After RESET is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not floating) for a minimum time of t Fig 6. RESET switches from HIGH to LOW SSTUB32865_3 Product data sheet ...
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... NXP Semiconductors PARIN CLOCK (1) This function holds the error for two cycles. For details, see switches from LOW to HIGH”. Fig 7. Parity logic diagram SSTUB32865_3 Product data sheet 1.8 V DDR2-800 registered buffer with parity Section 7 “Functional description” Rev. 03 — 27 March 2007 ...
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... NXP Semiconductors 8. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current O I continuous current through ...
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... NXP Semiconductors 10. Characteristics Table 10. Characteristics Over recommended operating conditions, unless otherwise noted. Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I supply current DD I dynamic operating current per MHz clock only; RESET = V DDD C input capacitance i Z output impedance ...
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... NXP Semiconductors Table 11. Timing requirements Over recommended operating conditions, unless otherwise noted. Symbol Parameter f clock frequency clock t pulse width W t differential inputs active time ACT t differential inputs inactive time INACT t set-up time su t hold time h [1] This parameter is not necessarily production tested. ...
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... NXP Semiconductors 11. Test information 11.1 Test circuit All input pulses are supplied by generators having the following characteristics: Pulse Repetition Rate (PRR) unless otherwise specified. The outputs are measured one at a time with one transition per measurement. CK inputs (1) C Fig 8. Load circuit (1) I Fig 9. Voltage and current waveforms ...
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... NXP Semiconductors Fig 11. Voltage waveforms; set-up and hold times Fig 12. Voltage waveforms; propagation delay times (clock to output) Fig 13. Voltage waveforms; propagation delay times (reset to output) SSTUB32865_3 Product data sheet input V ref V = 600 mV 0.5V . ref 250 mV (AC voltage levels) for differential inputs. V ...
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... NXP Semiconductors 11.2 Output slew rate measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 14. Load circuit, HIGH-to-LOW slew measurement Fig 15. Voltage waveforms, HIGH-to-LOW slew rate measurement (1) C Fig 16. Load circuit, LOW-to-HIGH slew measurement Fig 17 ...
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... NXP Semiconductors 11.3 Error output load circuit and voltage measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 18. Load circuit, error output measurements Fig 19. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to Fig 20. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect ...
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... NXP Semiconductors Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to SSTUB32865_3 Product data sheet timing V ICR inputs t LH output waveform 2 clock inputs Rev. 03 — 27 March 2007 SSTUB32865 1.8 V DDR2-800 registered buffer with parity V V i(p-p) ICR 002aaa503 © NXP B.V. 2007. All rights reserved. ...
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... NXP Semiconductors 12. Package outline TFBGA160: plastic thin fine-pitch ball grid array package; 160 balls; body 0.7 mm ball A1 index area ball index area 2 DIMENSIONS (mm are the original dimensions) A UNIT max 0.35 0.80 0.45 mm 1.15 0.25 0.65 0.35 OUTLINE VERSION IEC - - - SOT802-2 Fig 22. Package outline SOT802-2 (TFBGA160) ...
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... NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... Document ID Release date SSTUB32865_3 20070327 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 10 SSTUB32865_2 20060922 SSTUB32865_1 ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 8 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 Functional information . . . . . . . . . . . . . . . . . . . 9 7.3 Functional differences to SSTU32864 . . . . . . 10 7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, DCS2, DCS3, CSGATEEN) ...