SSTUB32865ET/G,518 NXP Semiconductors, SSTUB32865ET/G,518 Datasheet - Page 17

• Manufacturer Part Number: SSTUB32865ET/G,518
• Description: IC REG BUFFER 28BIT 160TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUB32865ET/G,518

• Logic Type: 1:2 Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-TFBGA
• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 2V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 160
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3542-2; 935281691518; SSTUB32865ET/G-T

NXP Semiconductors
Table 11.
Over recommended operating conditions, unless otherwise noted.
[1]
[2]
[3]
Table 12.
Over recommended operating conditions, unless otherwise noted.
[1]
[2]
Table 13.
Over recommended operating conditions, unless otherwise noted.
SSTUB32865_3
Product data sheet
Symbol
f
t
t
t
t
t
Symbol
f
t
t
t
t
t
t
Symbol
dV/dt_r
dV/dt_f
dV/dt_
clock
W
ACT
INACT
su
h
max
PDM
LH
HL
PLH
PDMSS
PHL
This parameter is not necessarily production tested.
Data inputs must be active below a minimum time of t
Data and clock inputs must be held at valid levels (not floating) a minimum time of t
Includes 350 ps of test-load transmission line delay.
This parameter is not necessarily production tested.
Timing requirements
Switching characteristics
Output edge rates
Parameter
clock frequency
pulse width
differential inputs active time
differential inputs inactive time
set-up time
hold time
Parameter
maximum input clock frequency
peak propagation delay
LOW to HIGH delay time
HIGH to LOW delay time
LOW-to-HIGH propagation delay
simultaneous switching peak
propagation delay
HIGH-to-LOW propagation delay
Parameter
rising edge slew rate
falling edge slew rate
absolute difference between dV/dt_r
and dV/dt_f
Rev. 03 — 27 March 2007
Conditions
CK, CK HIGH or LOW
Chip Select; DCS0, DCS1
valid before clock
switching
Data; Dn valid before
clock switching
PARIN; PARIN before CK
and CK
input to remain valid after
clock switching
PARIN after CK and CK
Conditions
CK and CK to output
CK and CK to PTYERR
CK and CK to PTYERR
from RESET to PTYERR
CK and CK to output
RESET to output
Conditions
ACT(max)
after RESET is taken HIGH.
1.8 V DDR2-800 registered buffer with parity
INACT(max)
[1][2]
[1][3]
[1][2]
[1]
after RESET is taken LOW.
Min
-
1
-
-
0.6
0.5
0.5
0.4
0.4
Min
450
1.1
1.2
1
-
-
-
Min
1
1
-
SSTUB32865
Typ
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
Typ
-
-
-
© NXP B.V. 2007. All rights reserved.
Max
450
-
10
15
-
-
-
-
-
Max
-
1.5
3
3
3
1.6
3
Max
4
4
1
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
ns
ns
ns
ns
ns
ns
Unit
V/ns
V/ns
V/ns
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