SSTUB32865ET/G,518 NXP Semiconductors, SSTUB32865ET/G,518 Datasheet - Page 11

• Manufacturer Part Number: SSTUB32865ET/G,518
• Description: IC REG BUFFER 28BIT 160TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUB32865ET/G,518

• Logic Type: 1:2 Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-TFBGA
• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 2V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 160
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3542-2; 935281691518; SSTUB32865ET/G-T

NXP Semiconductors
SSTUB32865_3
Product data sheet
Fig 4. RESET switches from LOW to HIGH
PTYERR
(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a minimum
RESET
PARIN
DCSn
Dn
CK
CK
Qn
(1)
time of t
7.3.4 Power-up sequence
ACT(max)
HIGH, LOW, or Don't care
to avoid false error.
The reset function for the SSTUB32865 is similar to that of the SSTU32864 except that
the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive
clock cycles.
t
ACT
m
HIGH or LOW
t
PDM
Rev. 03 — 27 March 2007
, t
CK to Q
PDMSS
t
su
m + 1
CK to PTYERR
t
h
t
t
su
PHL
1.8 V DDR2-800 registered buffer with parity
m + 2
t
h
m + 3
CK to PTYERR
SSTUB32865
t
PHL
, t
PLH
© NXP B.V. 2007. All rights reserved.
m + 4
002aaa983
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