AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 6

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Write Operation Status . . . . . . . . . . . . . . . . . . . . 49
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 53
DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . 54
DC CHARACTERISTICS (Continued) . . . . . . . . 55
4
Configuration Register Write Command ........................36
Common Flash Interface (CFI) Command ......................36
SecSi Sector Entry Command ...............................................38
Password Program Command .............................................38
Password Verify Command ..................................................38
Password Protection Mode Locking Bit Program
Command ..................................................................................38
Persistent Sector Protection Mode Locking Bit
Program Command ................................................................39
SecSi Sector Protection Bit Program Command ...........39
PPB Lock Bit Set Command .................................................39
DYB Write Command ...........................................................39
Password Unlock Command ...............................................39
PPB Program Command ....................................................... 40
DYB Write ............................................................................... 40
PPB Lock Bit Set ..................................................................... 40
DYB Status ................................................................................ 40
PPB Lock Bit Status ................................................................ 40
Non-volatile Protection Bit Program And Erase
Flow ............................................................................................ 40
DQ7: Data# Polling ................................................................ 49
RY/BY#: Ready/Busy# ........................................................... 49
DQ6: Toggle Bit I ................................................................... 50
DQ2: Toggle Bit II .................................................................. 50
Reading Toggle Bits DQ6/DQ2 ............................................51
DQ5: Exceeded Timing Limits ..............................................51
OPERATING RANGES ...........................................................53
Zero Power Flash ....................................................................55
Table 19. Memory Array Command
Definitions (x32 Mode) ................................................................... 42
Table 20. Sector Protection Command
Definitions (x32 Mode) ................................................................... 43
Table 21. Memory Array Command
Definitions (x16 Mode) .................................................................... 45
Table 22. Sector Protection Command
Definitions (x16 Mode) .................................................................... 47
Figure 6. Data# Polling Algorithm .............................................. 50
Figure 7. Toggle Bit Algorithm ...................................................... 51
Table 23. Write Operation Status ............................................... 52
Figure 8. Maximum Negative Overshoot Waveform ............ 53
Figure 9. Maximum Positive Overshoot Waveform............... 53
Table 24. CMOS Compatible ........................................................ 54
Figure 10. ICC1 Current vs. Time
(Showing Active and Automatic Sleep Currents) .................. 55
Am29BDD160G
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 57
Erase and Programming Performance . . . . . . . . . 71
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 72
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 73
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . 74
KEY TO SWITCHING WAVEFORMS .............................56
SWITCHING WAVEFORMS ...............................................56
VCC and VIO Power Up ........................................................57
Asynchronous Read Operations ........................................ 58
Burst Mode Read .....................................................................59
Hardware Reset (RESET#) ................................................... 62
Erase/Program Operations
Alternate CE# Controlled Erase/Program
Operations ................................................................................. 69
LATCHUP CHARACTERISTICS .........................................71
PQFP AND FORTIFIED BGA PIN CAPACITANCE ....71
DATA RETENTION ................................................................71
PQR080-80-Lead Plastic Quad Flat Package ....................72
LAA 080-80-ball Fortified Ball Grid
Array (13 x 11 mm) .....................................................................73
Figure 11. Typical Icc1 vs. Frequency ............................................. 55
Figure 12. Test Setup ....................................................................... 56
Table 25. Test Specifications ......................................................... 56
Figure 13. Input Waveforms and Measurement
Levels .................................................................................................... 56
Figure 14. VCC and VIO Power-up Diagram............................ 57
Figure 15. Conventional Read Operations Timings................. 60
Figure 16. Burst Mode Read (x32 Mode).................................... 60
Figure 17. Asynchronous Command Write Timing.................. 61
Figure 18. Synchronous Command Write/Read Timing ......... 61
Figure 19. Reset Timing.................................................................... 63
Figure 20. WP# Timing ................................................................... 63
Figure 21. Program Operation Timings ..................................... 65
Figure 22. Chip/Sector Erase Operation Timings ................... 65
Figure 23. Back-to-Back Cycle Timing ........................................ 66
Figure 24. Data# Polling Timings (During Embedded
Algorithms) ........................................................................................ 66
Figure 25. Toggle Bit Timings (During Embedded
Algorithms) ......................................................................................... 67
Figure 26. DQ2 vs. DQ6 for Erase and Erase Suspend
Operations .......................................................................................... 67
Figure 27. Synchronous Data Polling Timing/Toggle
Bit Timing............................................................................................. 68
Figure 28. Sector Protect/Unprotect Timing Diagram.......... 68
Figure 29. Alternate CE# Controlled Write Operation
Timings ................................................................................................. 70
.................... 64