AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 22

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Burst Access Timing Control
In addition to the IND/WAIT# signal control, burst
controls exist in the Control Register for initial access
delay, delivery of data on the CLK edge, and the
length of time data is held.
Initial Burst Access Delay Control
The Am29BDD160 contains options for initial access
delay of a burst access. The initial access delay has
no effect on asynchronous read operations.
Burst Initial Access Delay is defined as the number of
clock cycles that must elapse from the first valid
clock edge after ADV# assertion (or the rising edge
of ADV#) until the first valid CLK edge when the data
is valid.
The burst access is initiated and the address is
latched on the first rising CLK edge when ADV# is
active or upon a rising ADV# edge, whichever comes
first. (See Table 8 describes the initial access delay
configurations.) If the Clock Configuration bit in the
Control Register is set to falling edge (CR6 = 0), the
definition remains the same for the initial delay set-
Notes:
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 1 or three clock cycles
4. CR [13-10] = 2 or four clock cycles
5. CR [13-10] = 3 or Five clock cycles
20
Figure 3. Initial Burst Delay Control
Am29BDD160G
ting withe the exception that data is valid after the
falling edge.
CR13
0
0
0
0
0
0
0
0
Table 8. Burst Initial Access Delay
CR12
0
0
0
0
1
1
1
1
CR11
0
0
1
1
0
0
1
1
CR10
0
1
0
1
0
1
0
1
Initial Burst Access
54D, 64C, 65A
(CLK cycles)
2
3
4
5
6
7
8
9