AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 46

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Program/Erase Resume
Unlock Bypass Program
Autoselec
Unlock Bypass CFI (14,
Configuration Register
Configuration Register
Legend:
BA = Address of the bank that is being switched to autose-
PA = Program Address (A18:A0). Addresses latch on the
PD = Program Data (DQ31:DQ0) written to location PA.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles
44
Accelerated Program
Command (Notes)
Unlock Bypass Entry
Unlock Bypass Erase
Unlock Bypass Reset
CFI Query (14, 15)
t (7)
lect mode, is in bypass mode, or is being erased. Deter-
mined by A18 and A17, see Tables 11 and 12 for more
detail.
falling edge of the WE# or CE# pulse, whichever hap-
pens later
Data latches on the rising edge of WE# or CE# pulse,
whichever happens first.
Program/Erase
Suspend (12)
Sector Erase
Verify (15)
Chip Erase
Write (17)
Reset (6)
Read (5)
Program
(13)
(16)
(18)
(18)
(18)
(18)
18)
Manufactur
Device ID
er ID
(11)
Table 19. Memory Array Command Definitions (x32 Mode)
Cycles
1
1
4
6
4
6
6
1
1
1
2
3
4
3
2
2
1
2
Addr Data Addr Data
XXX
555
555
555
555
555
555
555
555
RA
BA
BA
XX
XX
XX
XX
XX
55
First
RD
AA
AA
AA
AA
AA
B0
A0
AA
AA
AA
A0
F0
30
98
80
98
90
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
XX
XX
PA
PA
Second
Am29BDD160G
55
55
55
55
55
PD
55
55
55
PD
10
00
(BA)55
Addr
555
555
555
555
555
555
555
5
Third
RA = Read Address (A18:A0).
RD = Read Data (DQ31:DQ0) from location RA.
SA = Sector Address (A18:A11) for verifying (in autoselect
WD = Write Data. See “Configuration Register” definition
X
4. During unlock cycles, (lower address bits are 555 or
Bus Cycles (Notes 1–4)
mode), erasing, or applying security commands.
= Don’t care
are write operations.
2AAh as shown in table) address bits higher than A11
(except where BA is required) and data bits higher than
DQ7 are don’t cares.
Data
90
90
A0
80
80
C6
D0
20
(BA)XX
(BA)X0
(BA)X0
Addr
555
555
PA
XX
0
1
Fourth
Data
WD
PD
AA
AA
RD
01
7E
(BA)X0E
Addr
2AA
2AA
Fifth
Data
08
55
55
(BA)X0F
Addr
555
SA
Sixth
Data
00/
01
10
30