AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 17

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Caution:
SET# pin also resets the device to the read mode
and floats the data I/O pins. Furthermore, entering
I
erroneous data in the address locations being oper-
ated on at the time of the RESET# pulse. These
locations require updating after the device resumes
standard operations. Refer to the “RESET#: Hard-
ware Reset Pin” section for further discussion of the
RESET# pin and its functions
RESET#: Hardware Reset Pin
The RESET# pin is an active low signal that is used
to reset the device under any circumstances. A logic
“0” on this pin forces the device out of any mode
that is currently executing back to the reset state.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the
device. To avoid a potential bus contention during a
system reset, the device is isolated from the DQ data
bus by tri-stating the data output pins for the dura-
tion of the RESET pulse. All pins are “don’t care”
during the reset operation.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains low until the reset
operation is internally complete. This action requires
between 1 µs and 7µs for either Chip Erase or Sector
Erase. The RY/BY# pin can be used to determine
when the reset operation is complete. Otherwise,
allow for the maximum reset time of 11 µs. If RE-
SET# is asserted when a program or erase operation
is not executing (RY/BY# = “1”), the reset operation
will complete within 500 ns. Since the Am29BDD160
is a Simultaneous Operation device the user may
read a bank after 500 ns if the bank was in the read/
reset mode at the time RESET# was asserted. If one
of the banks was in the middle of either a program or
erase operation when RESET# was asserted, the
user must wait 11 µs before accessing that bank.
Asserting RESET# during a program or erase opera-
tion leaves erroneous data stored in the address
locations being operated on at the time of device re-
set. These locations need updating after the reset
CC7
during a program or erase operation will leave
entering the standby mode via the RE-
.
Am29BDD160G
operation is complete. See Figure 19 for timing spec-
ifications.
Asserting RESET# active during V
up is required to guarantee proper device initializa-
tion until V
state voltages.
Output Disable Mode
See Table 1 Device Bus Operation for OE# Operation
in Output Disable Mode.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
m e n t t o a u to m a t i c a l l y m a tc h a d ev i c e t o b e
programmed with its corresponding programming al-
gorithm. However, the autoselect codes can also be
accessed in-system through the command register.
When using programming equipment, the au-
toselect mode requires V
Address pins A6, A1, and A0 must be as shown
in Table 12 (top boot devices) or Table 13 (bot-
tom boot devices). In addition, when verifying
sector protection, the sector address must ap-
pear on the appropriate highest order address
bits (see Tables 11 and 12). See Table 5 shows
the remaining address bits that are don’t care.
When all necessary bits have been set as re-
quired, the programming equipment may then
read the corresponding identifier code on DQ7–
DQ0.
To access the autoselect codes in-system, the
host system can issue the autoselect command
via the command. This method does not re-
quire V
details on using the autoselect mode.
I D
. See “Command Definitions” for
CC
and V
IO
have reached their steady
ID
on address pin A9.
CC
a nd V
IO
power-
15