AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 35

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Command Definitions
Writing specific address and data commands or se-
quences into the command register initiates device
operations. Tables
command sequences. Writing incorrect address
and data values or writing them in the improper
sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched
on the rising edge of WE# or CE#, whichever hap-
pens first. Refer to the
timing diagrams.
Reading Array Data in Non-burst Mode
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See
for more information on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the
programming of the PPB Lock Bit for a given sector
can be verified by writing a PPB Lock Bit status verify
command to the device.
See also
in the
information. See the
sume Command
this mode.
Sector Erase and Program Suspend Command
5Ah
5Bh
57h
58h
59h
Key to Switching Waveforms
Asynchronous Read Operation (Non-Burst)
Table 17. CFI Primary Vendor-Specific Extended Query (Sheet 3 of 3)
sections for more information on
18-21
Sector Erase and Program Re-
AEh
B0h
B2h
B4h
B6h
AC Characteristics
section.
define the valid register
section for more
0002h
0000h
0000h
000Fh
001Fh
section for
Am29BDD160G
Bank Organization (1 byte)
00 = If data at 4Ah is zero
XX = Number of banks
Bank 1 Region Information (1 byte)
XX = Number of Sectors in Bank 1
Bank 2 Region Information (1 byte)
XX = Number of Sectors in Bank 2
Bank 3 Region Information (1 byte)
XX = Number of Sectors in Bank 3
Bank 4 Region Information (1 byte)
XX = Number of Sectors in Bank 4
The
Reading Array Data in Burst Mode
The device is capable of very fast Burst mode read
operations. The configuration register sets the read
configuration, burst order, frequency configuration,
and burst length.
Upon power on, the device defaults to the asynchro-
nous mode. In this mode, CLK, and ADV# are
ignored. The device operates like a conventional
Flash device. Data is available t
after address becomes stable, CE# become as-
serted. The device enters the burst mode by
enabling synchronous burst reads in the configura-
tion register. The device exits burst mode by
disabling synchronous burst reads in the configura-
tion register. (See
The RESET# command will not terminate the Burst
mode. System reset (power on reset) will terminate
the Burst mode.
The device has the regular control pins, i.e. Chip En-
able (CE#), Write Enable (WE#), and Output Enable
(OE#) to control normal read and write operations.
Moreover, three additional control pins have been
added to allow easy interface with minimal glue logic
to a wide range of microprocessors / microcontrollers
for high performance Burst read capability. These
additional pins are Address Valid (ADV#) and Clock
(CLK). CE#, OE#, and WE# are asynchronous (rela-
tive to CLK). The Burst mode read operation is a
synchronous operation tied to the edge of the clock.
The microprocessor / microcontroller supplies only
the initial address, all subsequent addresses are au-
tomatically generated by the device with a timing
defined by the Configuration Register definition. The
Burst read cycle consists of an address phase and a
corresponding data phase.
During the address phase, the Address Valid (ADV#)
pin is asserted (taken Low) for one clock period. To-
gether with the edge of the CLK, the starting burst
address is loaded into the internal Burst Address
Counter. The internal Burst Address Counter can be
configured to either the Linear modes (See “Initial
Access Delay Configuration”).
Command
Definitions).
ACC
/ t
CE
nanoseconds
33