AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 49

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Program/Erase Resume
Unlock Bypass Program
Autoselec
Unlock Bypass CFI (14,
Configuration Register
Configuration Register
Legend:
BA = Address of the bank that is being switched to autose-
PA = Program Address (A18:A-1). Addresses latch on the
PD = Program Data (DQ15:DQ0) written to location PA.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
Accelerated Program
Unlock Bypass Erase
Unlock Bypass Reset
Command (Notes)
Unlock Bypass Entry
CFI Query (14, 15)
t (7)
lect mode, is in bypass mode, or is being erased. Deter-
mined by A18 and A17, see Tables 11 and 12 for more
detail.
falling edge of the WE# or CE# pulse, whichever hap-
pens later.
Data latches on the rising edge of WE# or CE# pulse,
whichever happens first.
Program/Erase
Suspend (12)
Sector Erase
Chip Erase
Verify (15)
Write (17)
Reset (6)
Read (5)
Program
(13)
(16)
(18)
(18)
(18)
(18)
18)
Manufactur
Device ID
er ID
(11)
Table 21. Memory Array Command Definitions (x16 Mode)
Cycles
1
1
4
6
4
6
6
1
1
1
2
3
4
3
2
2
1
2
Addr Data Addr Data
XXX
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
RA
BA
BA
AA
XX
XX
XX
XX
XX
First
RD
AA
AA
AA
AA
AA
B0
30
98
A0
AA
AA
AA
A0
80
98
90
F0
555
555
555
555
555
555
555
555
XX
XX
PA
PA
Second
Am29BDD160G
PD
PD
55
55
55
55
55
55
55
55
10
00
(BA)55
Addr
AAA
AAA
AAA
AAA
AAA
AAA
AAA
5
Third
RA = Read Address (A18:A-1).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (A18:A11) for verifying (in autoselect
WD = Write Data. See “Configuration Register” definition for
X = Don’t care
3. Shaded cells in table denote read cycles. All other cycles
4. During unlock cycles, (lower address bits are AAA or
Bus Cycles (Notes 1–4)
mode), erasing, or applying security commands
specific write data. Data latched on rising edge of WE#.
are write operations.
555h as shown in table) address bits higher than A11
Data
A0
C6
D0
90
90
80
80
20
(BA)X0
(BA)X0
(BA)XX
Addr
AAA
AAA
XX
PA
0
2
Fourth
Data
WD
RD
01
7E
PD
AA
AA
(BA)X1C
Addr
555
555
Fifth
Data
08
55
55
(BA)X1E
Addr
555
SA
Sixth
Data
00/
01
10
30
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