AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 55

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Figure 7 shows the toggle bit algorithm in flowchart
form, and the section
explains the algorithm. See also the
I
diagram. Figure 25 shows the differences between
DQ2 and DQ6 in graphical form. Figure 27 shows the
timing diagram for synchronous DQ2 toggle bit sta-
tus.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 25 for the following discussion.
Whenever the system initially begins reading toggle
bit status, it must perform two immediately consecu-
tive reads of DQ7–DQ0 to determine whether a
toggle bit is toggling. Typically, the system would
note and store the value of the toggle bit after the
first read. After the second read, the system would
compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The sys-
tem can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two immediately consecu-
tive read cycles, the system determines that the
toggle bit is still toggling, the system also should
note whether the value of DQ5 is high (see the sec-
tion on DQ5). If it is, the system should then
determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just
as DQ5 went high. If the toggle bit is no longer tog-
gling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully,
and the system must write the reset command to re-
turn to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5
has not gone high. The system may continue to
monitor the toggle bit and DQ5 through successive
read cycles, determining the status as described in
the previous paragraph. Alternatively, it may choose
to perform other system tasks. In this case, the sys-
tem must start at the beginning of the algorithm
when it returns to determine the status of the opera-
tion (top of Figure 7).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time
has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1.” This is a
failure condition that indicates the program or erase
cycle was not successfully completed.
subsection. Figure 25 shows the toggle bit timing
Reading Toggle Bits DQ6/DQ2
DQ6: Toggle Bit
Am29BDD160G
Note:
1. Read toggle bit with two immediately consecutive reads
2. Recheck toggle bit because it may stop toggling as DQ5
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition,
the device halts the operation, and when the opera-
tion has exceeded the timing limits, DQ5 produces a
“1.”
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
an erase operation has begun. (The sector erase
timer does not apply to the chip erase command.) If
to determine whether or not it is toggling. See text.
changes to “1”. See text.
Figure 7. Toggle Bit Algorithm
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