AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 19

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Synchronous (Burst) Read Operation
The Am29BDD160 is capable of performing burst
read operations to improve total system data
throughput. The device is available in three burst
modes of operation: linear and burst mode. 2, 4 and
8 double word (x32) and 4 and 8 word (x16) ac-
cesses are configurable as either sequential burst
accesses. 16 and 32 word (x16) accesses are only
configurable as linear burst accesses. Additional op-
tions for all burst modes include initial access delay
configurations (2–16 CLKs) Device configuration for
burst mode operation is accomplished by writing the
Configuration Register with the desired burst config-
uration information. Once the Configuration Register
is written to enable burst mode operation, all subse-
quent reads from the array are returned using the
burst mode protocols. Like the main memory access,
the SecSi Sector memory is accessed with the same
burst or asynchronous timing as defined in the Con-
f ig u ra t io n Re g i s t e r. H ow e v e r, t h e u s e r m u s t
recognize that continuous burst operations past the
256 byte SecSi boundary returns invalid data.
Burst read operations occur only to the main flash
memory arrays. The Configuration Register and pro-
tection bits are treated as single cycle reads, even
when burst mode is enabled. Read operations to
(Independent of the WORD#
Eight Linear Data Transfers
Data Transfer Sequence
Two Linear Data Transfers,
Four Linear Data Transfers
(x32 only)
Table 6. 16-Bit and 32-Bit Linear and Burst Data Order (Sheet 1 of 2)
pin)
Am29BDD160G
Output Data Sequence (Initial Access Address)
1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001)
2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010)
3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011)
4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100)
5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101)
6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110)
7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111)
0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000)
0-1-2-3 (A0:A-1/A1-A0 = 00)
1-2-3-0 (A0:A-1/A1-A0 = 01)
3-0-1-2 (A0:A-1/A1-A0 = 11)
these locations results in the data remaining valid
while OE# is at V
cycles applied to the device.
Linear Burst Read Operations
Linear burst read mode reads either 4, 8, 16, or 32
words (1 word = 16 bits), depending upon the Con-
figuration Register option. If the device is configured
with a 32 bit interface (WORD# = V
cess is comprised of 4 clocked reads for 8 words and
16 clocked reads for 32 words (See Table 6 for all
valid burst output sequences). The number of
clocked reads is doubled when the device is config-
ured in the 16-bit data bus mode (WORD# = V
The IND/WAIT# pin transitions active (V
the last transfer of data during a linear burst read
before a wrap around, indicating that the system
should initiate another ADV# to start the next burst
access. If the system continues to clock the device,
the next access wraps around to the starting address
of the previous burst access. The IND/WAIT# signal
remains inactive (floating) when not active. See
Table 6 for a complete 32 and 16 bit data bus inter-
face order. 16 and 32 word options are restricted to
sequential burst accesses, only.
2-3-0-1 (A:A-1/A1-A0 = 10)
0-1 (A0 = 0)
1-0 (A0 = 1)
(x16)
IL
, regardless of the number of CLK
IH
), the burst ac-
IL
) during
IL
17
).