AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 52

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

RD(0) = Read Data DQ0 protection indicator bit. If pro-
RD(1) = Read Data DQ1 protection indicator bit. If pro-
SA = Sector Address where security command applies. Ad-
1. 1. See Table 1 for description of bus operations.
2. 2.All values are in hexadecimal.
3. 3.Shaded cells in table denote read cycles. All other
4. During unlock cycles, (lower address bits are AAA or
5. The reset command returns the device to reading the
6. The fourth cycle programs the addressed locking bit. The
7. Data is latched on the rising edge of WE#.
8. The entire four bus-cycle sequence must be entered for
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tected, DQ0 = 1, if unprotected, DQ0 = 0.
tected, DQ1 = 1, if unprotected, DQ1 = 0.
dress bits A18:A11 uniquely select any sector.
cycles are writer operations.
555h as shown in the table) address bits higher that A11
(except where BA is required) and data bits higher than
DQ7 are dont’s cares.
array.
fifth and sixth cycles are used to validate whether the bit
is fully programmed. If DQ0 (in the sixth cycle) reads 0,
the program command must be issued and verified
again.
each portion of the password. PWA (0-3) represent the
Am29BDD160G
SL = Persistent Protection Mode Lock Address (A5–A0) is
WP = PPB Address (A5–A0) is (111X10)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
9. The fourth cycle erases all PPBs. The fifth and sixth
10. Before issuing the erase command, all PPBs should be
11. In the fourth cycle, 00h indicates PPB set; 01h indicates:
12. The status of additional PPBs and DYBs may be read
(010X10)
four addresses over which the password is stored. PWD
(0-3) represent the four word data that comprise the
password.
cycles are used to validate whether the bits are fully
erased. If DQ0 (in the sixed cycle) reads 1, the erase
command must be issued and verified again.
programmed in order to prevent over-erasure of PPBs.
PPB not set.
(following the fourth cycle) without reissuing the entire
command sequence