AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 23

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Burst CLK Edge Data Delivery
The Am29BDD160 is capable of delivering data on
either the rising or falling edge of CLK. To deliver
data on the rising edge of CLK, bit 6 in the Control
Register (CR6) is set to 1. To deliver data on the fall-
ing edge of CLK, bit 6 in the Control Register is
cleared to 0. The default configuration is set to the
rising edge.
Burst Data Hold Control
The device is capable of holding data for one CLKs.
The default configuration is to hold data for one CLK
and is the only valid state.
Asserting RESET# During A Burst Access
If RESET# is asserted low during a burst access, the
burst access is immediately terminated and the de-
vice defaults back to asynchronous read mode. Refer
to
on the RESET# function.
Configuration Register
The Am29BDD160 contains a Configuration Register
for configuring read accesses. The Configuration
Register is accessed by the Configuration Register
Read and the Configuration Register Write com-
mands. The Configuration Register does not occupy
Configuration Register
CR15 = Read Mode (RM)
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
CR14 = Reserved for Future Enhancements
These bits are reserved for future use. Set these bits to “0”.
CR13–CR10 = Initial Burst Access Delay Configuration (IAD3-IAD0)
Speed Options 54D, 64C, 65A:
0000 = 2 CLK cycle initial burst access delay
0001 = 3 CLK cycle initial burst access delay
0010 = 4 CLK cycle initial burst access delay
0011 = 5 CLK cycle initial burst access delay
0100 = 6 CLK cycle initial burst access delay
0101 = 7 CLK cycle initial burst access delay
0110 = 8 CLK cycle initial burst access delay
0111 = 9 CLK cycle initial burst access delay—Default
CR9 = Data Output Configuration (DOC) 0 = Hold Data for 1-CLK cycle—Default 1 = Reserved
RESET#: Hardware Reset Pin
CR15
CR7
RM
BS
Reserved
CR14
CR6
CC
Table 9. Configuration Register Definitions
Reserved
for more information
CR13
IAD3
CR5
Reserved
CR12
CR4
IAD2
Am29BDD160G
any addressable memory location, but rather, is ac-
cessed by the Configuration Register commands. The
Configuration Register is readable any time, how-
ever, writing the Configuration Register is restricted
to times when the Embedded Algorithm™ is not ac-
tive. If the user attempts to write the Configuration
Register while the Embedded Algorithm™ is active,
the write operation is ignored and the contents of the
Configuration Register remain unchanged.
The Configuration Register is a 16 bit data field
which is accessed by DQ15–DQ0. Data on
DQ31–DQ16 is ignored during a write operation
when WORD# = V
DQ31–DQ16 returns all zeroes. Table 9 shows
the Configuration Register. Also, Configuration
Register reads operate the same as Autoselect
command reads. When the command is issued,
the bank address is latched along with the
command. Reads operations to the bank that
was specified during the Configuration Register
read command return Configuration Register
contents. Read operations to the other bank re-
turn flash memory data. Either bank address is
permitted when writing the Configuration Reg-
ister read command.
Reserved
CR3
CR11
IAD1
CR2
BL2
CR10
IAD0
IL
. During a read operation,
CR1
BL1
DOC
CR9
CR0
BL0
CR8
WC
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